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4155e?aero?06/04 features functionally and pin compatible with the atmel commercial and military at40k series ultra high performance ? system speeds 60 mhz ? array multipliers > 32 mhz ? 18 ns flexible sram ? internal tri-state capability in each cell freeram ? ? flexible, single/dual port, sync/async 18 ns sram ? 18432 bits of distributed sram independent of logic cells for at40kel040 384 pci compliant i/os ? programmable output drive ? fast, flexible array access facilitates pin locking 8 global clocks ? fast, low skew clock distribution ? programmable rising/falling edge transitions ? distributed clock shutdown capability for low power management ? global reset/asynchronous reset options ? 4 additional dedicated pci clocks cache logic ? dynamic full/partial reconfigurability in-system ? unlimited reprogrammability via serial or parallel modes ? enables adaptive designs ? enables fast vector multiplier updates ? quick-change ? tools for fast, easy design changes package options ?mqfpf160 ?mqfpf256 industry-standard design tools ? seamless integration (libraries, interface, full back-annotation) with exemplar ? , mentor ? , synplicity ? ? timing driven placement & routing ? automatic/interactive multi-chip partitioning ? fast, efficient synthesis ? over 75 automatic component generators create 1000s of reusable, fully deterministic logic and ram functions intellectual property cores ? fir filters, uarts, pci, fft and other system level functions easy migration to atmel gate arrays for high volume production supply voltage 3.3v 200 krads (tm 1019.5) latch-up threshold higher than 70 mev.cm 2 / mg built-in seu hardening quality grades ? qml -q and -v with smd 5962-03250 ? escc b with 9301/051 design tools ? design kit (at40kel-dk) including: mother board daughter board for mqfpf160 at17 series configuration memory isp download cable system designer cd-rom (including ids tool) ? additional daughter board variant: atdh40d256m: for mqfpf256 rad hard reprogrammable fpgas with freeram ? at40kel040
2 at40kel040 4155e?aero?06/04 *** note: 1. packages with fck will have 8 less clocks. description the at40kel040 is a fully pci-compliant, sram-based fpga with distributed 18 ns programmable synchronous/asynchronous, dual port/single port sram, 8 global clocks, cache logic ability (partially or fully reconfigurable without loss of data), automatic com- ponent generators, and 50,000 usable gates. i/o counts range from 128 to 384 in aero- space standard packages and support 3.3v. the at40kel040 is designed to quickly implement high performance, large gate count designs through the use of synthesis and schematic-based tools used on a pc and sun ? platform. atmel?s design tools provide seamless integration with industry standard tools such as synplicity, modelsim, exemplar and viewlogic. see the ids datasheet for other supported tools. the at40kel040 can be used as a co-processor for high-speed (dsp/processor- based) designs by implementing a variety of compute-intensive, arithmetic functions. these include adaptive finite impulse response (fir) filters, fast fourier transforms (fft), convolvers, interpolators and discrete-cosine transforms (dct) that are required for video compression and decompression, encryption, convolution and other multime- dia applications. fast, flexible and efficient sram the at40kel040 fpga offers a patented distributed 11 - 13 ns sram capability where the ram can be used without losing logic resources. multiple independent, synchronous or asynchronous, dual port or single port ram functions (fifo, scratch pad, etc.) can be created using atmel?s macro generator tool. fast, efficient array and vector multipliers the at40kel040?s patented 8-sided core cell with direct horizontal, vertical and diago- nal cell-to-cell connections implements ultra fast array multipliers without using any bus- ing resources. the at40kel040?s cache logic capability enables a large number of design coefficients and variables to be implem ented in a very small amount of silicon, enabling vast improvement in system speed at much lower cost than conventional fpgas. cache logic design the at40kel040 is capable of implementing cache logic (dynamic full/partial logic reconfiguration, without loss of data, on-the-fly) for building adaptive logic and systems. as new logic functions are required, they can be loaded into the logic cache without los- ing the data already there or disrupting the operation of the rest of the chip; replacing or complementing the active logic. the at40kel040 can act as a reconfigurable co-pro- cessor. automatic component generators the at40kel040 fpga family is capable of implementing user-defined, automatically generated, macros in multiple designs; speed and functionality are unaffected by the macro orientation or density of the target device. this enables the fastest, most predict- able and efficient fpga design approach and minimizes design risk by reusing already table 1. at40kel040 device at40kel040 usable gates 40k - 50k rows x columns 48 x 48 cells 2,304 registers 3,048 (1) ram bits 2304 i/o (max) 384
3 at40kel040 4155e?aero?06/04 proven functions. the automatic component generators work seamlessly with industry- standard schematic and synthesis tools to cr eate the fastest, most efficient designs available. the patented at40kel040 series architecture employs a symmetrical grid of small yet powerful cells connected to a flexible busing network. independently controlled clocks and resets govern every column of cells. the array is surrounded by programmable i/o. devices offer 50,000 usable gates, and have 3,056 registers. at40k series fpgas uti- lize a reliable 0.35 single-poly, 4-metal cmos process and are 100% factory-tested. atmel?s pc- and workstation-based integrated development system (ids) is used to cre- ate at40kel040 series designs. multiple design entry methods are supported. the atmel architecture was developed to provide the highest levels of performance, functional density and design flexibility in an fpga. the cells in the atmel array are small, efficient and can implement any pair of boolean functions of (the same) three inputs or any single boolean function of four inputs. the cell?s small size leads to arrays with large numbers of cells, greatly multip lying the functionality in each cell. a simple, high-speed busing network provides fast, efficient communication over medium and long distances. at40kel040 configurator statistics extracted from configuration bits treams show that the maximum needed size is 1mbit. in order to keep the maximum number of pins assigned to signals, it is recommended to use a serial configuration interface. this is the reason why atmel proposes a 1mbit serial eeprom for configuring the at40kel040, the at17lv010-10dp which is also a 3.3v bias chip. it is packaged into a 28-pin dil flat pack 400mils wide. this memory has been tested for total dose under bias and unbiased conditions, exhib- iting far better results when unbiased; this is the reason why it is recommended to switch off the memory when it is not in the configuration mode. in addition, heavy ions tests have shown that the data stored in the memory cells are not corrupted eventhough errors may be detected while downloading the bitstream; this is the result of the data serialization from the parallel memory plan; therefore, it is recom- mended to use the fpga crc while configur ing it, and to resume the configuration when an error is detected.
4 at40kel040 4155e?aero?06/04 the symmetrical array at the heart of the atmel architecture is a symmetrical array of identical cells (figure 1). the array is continuous from one edge to the other, except for bus repeaters spaced every four cells (figure 2 on page 5). at the intersection of each repeater row and col- umn is a 32 x 4 ram block accessible by adjacent buses. the ram can be configured as either a single-ported or dual-ported ram (1) , with either synchronous or asynchro- nous operation. note: 1. the right-most column can only be used as single-port ram. figure 1. symmetrical array surrounded by i/o note: at40k has registered i/os. group enable every sector for tri-states on obuf?s. = i/o pad = at40k cell = repeater row = repeater column = freeram
5 at40kel040 4155e?aero?06/04 figure 2. floorplan (representative portion) (1) note: 1. repeaters regenerate signals and can connect any bus to any other bus (all path- ways are legal) on the same plane. each repeater has connections to two adjacent local-bus segments and two express-bus segments. this is done automatically using the integrated development system (ids) tool. rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rh = vertical repeater = horizontal repeater = core cell ram ram ram ram ram ram ram ram ram ram ram ram ram ram ram ram
6 at40kel040 4155e?aero?06/04 the busing network figure 3 on page 7 depicts one of five identical busing planes. each plane has three bus resources: a local-bus resource (the middle bus) and two express-bus (both sides) resources. bus resources are connected via repeaters. each repeater has connections to two adjacent local-bus segments and tw o express-bus segments. each local-bus segment spans four cells and connects to c onsecutive repeaters. each express-bus segment spans eight cells and ?leapfrogs? or bypasses a repeater. repeaters regener- ate signals and can connect any bus to any other bus (all pathways are legal) on the same plane. although not shown, a local bus can bypass a repeater via a programma- ble pass gate allowing long on-chip tri-state buses to be created. local/local turns are implemented through pass gates in the cell-bus interface (see following page). express/express turns are implemented through separate pass gates distributed throughout the array. some of the bus resource on the at40 kel040 is used as a dual-function resource. table 2 shows which buses are used in a dual-function mode and which bus plane is used. the at40kel040 software tools are designed to accommodate dual-function buses in an efficient manner. table 2. dual-function buses function type plane(s) direction comments cell output enable local 5 horizontal and vertical ram output enable express 2 vertical bus full length at array edge bus in first column to left of ram block ram write enable express 1 vertical bus full length at array edge bus in first column to left of ram block ram address express 1 - 5 vertical buses full length at array edge buses in second column to left of ram block ram data in local 1 horizontal ram data out local 2 horizontal clocking express 4 vertical bus half length at array edge set/reset express 5 vertical bus half length at array edge
7 at40kel040 4155e?aero?06/04 figure 3. busing plane (one of five) = local/local or express/express turn point = at40k/40kal = row repeater = column express bus local bus express bus at40kel040
8 at40kel040 4155e?aero?06/04 cell connections figure 4(a) depicts direct connections between a cell and its eight nearest neighbors. figure 4(b) shows the connections between a cell and five horizontal local buses (1 per busing plane) and five vertical local buses (1 per busing plane). figure 4. cell connections cel cel cel cel cel cel cel cel cel cel (a) cell-to-cell connections (b) cell-to-bus connections w x y z l wxyzl orthogonal direct connect diagonal direct connect ? ? ? ? ? ? ? ? ? ? horizontal busing plane vertical busing plane ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? plane 5 plane 4 plane 3 plane 2 plane 1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? plane 5 plane 4 plane 3 plane 2 plane 1
9 at40kel040 4155e?aero?06/04 the cell figure 5 depicts the at40kel040 cell. configuration bits for separate muxes and pass gates are independent. all permutations of programmable muxes and pass gates are legal. v n (v 1 -v 5 ) is connected to the vertical local bus in plane n. h n (h 1 -h 5 ) is con- nected to the horizontal local bus in plane n. a local/local turn in plane n is achieved by turning on the two pass gates connected to v n and h n . pass gates are opened to let sig- nals into the cell from a local bus or to drive a signal out onto a local bus. signals coming into the logic cell on one local bus plane can be switched onto another plane by opening two of the pass gates. this allows bus sign als to switch planes to achieve greater routability. up to five simultaneous local/local turns are possible. the at40kel040 fpga core cell is a highly configurable logic block based around two 3-input luts (8 x 1 rom), which can be combined to produce one 4-input lut. this means that any core cell can implement two functions of 3 inputs or one function of 4 inputs. there is a set/reset d flip-flop in every cell, the output of which may be tri-stated and fed back internally within the core cell. there is also a 2-to-1 multiplexer in every cell, and an upstream and gate in the ?front end? of the cell. this and gate is an impor- tant feature in the implementation of efficient array multipliers. figure 5. the cell with this functionality in each core cell, the core cell can be configured in several ?modes?. the core cell flexibility makes the at40kel040 architecture well suited to most digital design application areas (see figure 6). out out reset/set clock fb 10 z d q "1" nw ne se sw "1" "1" "1" "0" xwy x zwy "1" n e s w 8x1 lut 8x1 lut x y nw ne se sw n e s w v1 h1 v2 h2 v3 h3 v4 h4 v5 h5 "1" oe h oe v l pass gates x = diagonal direct connect or bus y = orthogonal direct connector bus w = bus connection z = bus connection fb = internal feed back
10 at40kel040 4155e?aero?06/04 figure 6. some single cell modes lut lut lut lut lut 2:1 mux lut lut dq dq q q (registered) dq dq synthesis mode. this mode is particularly important for the use of vhdl design. vhdl synthesis tools generally will produce as their output large amounts of random logic functions. having a 4-input lut structure gives efficient random logic optimization without the delays associated with larger lut structures. the output of any cell may be registered, tri-stated and/or fed back into a core cell. arithmetic mode is frequently used in many designs. as can be seen in the figure, the at40kel040 core cell can implement a 1-bit full adder (2-input adder with both carry in and carry out) in one core cell. note that the sum output in this diagram is registered. this output could then be tri-stated and/or fed back into the cell. dsp/multiplier mode. this mode is used to efficiently implement array multipliers. an array multiplier is an array of bitwise multipliers, each implemented as a full adder with an upstream and gate. using this and gate and the diagonal interconnects between cells, the array multiplier structure fits very well into the at40k architecture. counter mode. counters are fundamental to almost all digital designs. they are the basis of state machines, timing chains and clock dividers. a counter is essentially an increment by one function (i.e., an adder), with the input being an output (or a decode of an output) from the previous stage. a 1-bit counter can be implemented in one core cell. again, the output can be registered, tri-stated and/or fed back. tri-state/mux mode. this mode is used in many telecommunications applications, where data needs to be routed through more than one possible path. the output of the core cell is very often tri-statable for many inputs to many outputs data switching. a b c d a b c a b c d a b c en q q sum (registered) sum and/or product or carry product (registered) carry carry carry in and/or or and/or and/or
11 at40kel040 4155e?aero?06/04 ram 32 x 4 dual-ported ram blocks are dispersed throughout the array as shown in figure 7. a 4-bit input data bus connects to four horizontal local buses distributed over four sec- tor rows (plane 1). a 4-bit output data bus connects to four horizontal local buses dis- tributed over four sector rows (plane 2). a 5-bit input address bus connects to five vertical express buses in same column. a 5-bit output address bus connects to five ver- tical express buses in same column. ain (input address) and aout (output address) alternate positions in horizontally aligned ram blocks. for the left-most ram blocks, aout is on the left and ain is on the right. for the right-most ram blocks, ain is on the left and aout is tied off, thus it can only be configured as a single port. for single-ported ram, ain is the read/write address port and din is the (bi-directional) data port. right-most ram blocks can be used only fo r single-ported memories. wen and oen connect to the vertical express buses in the same column. figure 7. ram connections (one ram block) reading and writing of the 11 - 13 ns 32 x 4 dual-port freeram are independent of each other. reading the 32 x 4 dual-port ram is completely asynchronous. latches are transparent; when load is logic 1, data flows through; when load is logic 0, data is latched. these latches are used to synchronize write adress, write enable not, and din signals for a synchronous ram. each bit in the 32 x 4 dual-port ram is also a transpar- ent latch. the front-end latch and the memory latch together form an edge-triggered flip flop. when a nibble (bit = 7) is (write) addressed and load is logic 1 and we is logic 0, 32 x 4 ram clk din ain wen oen dout aout clk clk clk clk
12 at40kel040 4155e?aero?06/04 data flows through the bit. when a nibble is not (write) addressed or load is logic 0 or we is logic 1, data is latched in the nibble. the two clock muxes are controlled together; they both select clock (for a synchronous ram) or they both select ?1? (for an asynchronous ram). clock is obtained from the clock for the sector-column imme- diately to the left and immediately above the ram block. writing any value to the ram clear byte during configuration clears the ram (see the ? at40k/40kal configuration series? application note at www.atmel.com ). figure 8. ram logic figure 9 on page 13 shows an example of a ram macro constructed using at40kel040?s freeram cells. the macro shown is a 128 x 8 dual-ported asynchro- nous ram. note the very small amount of external logic required to complete the address decoding for the macro. most of the logic cells (core cells) in the sectors occu- pied by the ram will be unused: they can be used for other logic in the design. this logic can be automatically generated using the macro generators. write address din dout read address ?1? ?1? write enable not ram-clear byte dout 01 0 1 ? 1 ? clock load 5 ain aout wen din load latch load latch load latch clear 32 x 4 dual-port ram oe 4 4 5
13 at40kel040 4155e?aero?06/04 figure 9. ram example: 128 x 8 dual-ported ram (asynchronous) 2-to-4 decoder dout(4) dout(5) dout(6) dout(7) din dout wen oen ain aout din dout din dout wen oen din dout aout ain wen oen ain aout wen oen aout ain din dout aout ain wen oen din dout wen oen ain aout din dout aout ain wen oen din dout wen oen ain aout 2-to-4 decoder local buses express buses dedicated connections read address din(0) din(1) din(2) din(3) din(4) din(5) din(6) din(7) write address we dout(0) dout(1) dout(2) dout(3)
14 at40kel040 4155e?aero?06/04 clocking scheme there are eight global clock buses (gck1 - gck8) on the at40kel040 fpga. each of the eight dedicated global clock buses is connected to one of the dual-use global clock pins. any clocks used in the design should use global clocks where possible: this can be done by using assign pin locks to lock the clocks to the global clock locations. in addition to the eight global clocks, there are four fast clocks (fck1 - fck4), two per edge column of the array for pci specific ation. even the derived clocks can be routed through the global network. access points are provided in the corners of the array to route the derived clocks into the global clock network. the ids software tools handle derived clocks to global clock connections automatically if used. each column of an array has a ?column clock mux? and a ?sector clock mux?. the col- umn clock mux is at the top of every column of an array and the sector clock mux is at every four cells. the column clock mux is selected from one of the eight global clock buses. the clock provided to each sector column of four cells is inverted, non-inverted or tied off to ?0?, using the sector clock mux to minimize the power consumption in a sector that has no clocks. the clock can either come from the column clock or from the plane 4 express bus (see figure 10 on page 15). the extreme-left column clock mux has two additional inputs, fck1 and fck2, to provide fast clocking to left-side i/os. the extreme-right column clock mux has two additional inputs as well, fck3 and fck4, to provide fast clocking to right-side i/os. the register in each cell is triggered on a rising clock edge by default. before configura- tion on power-up, constant ?0? is provided to each register?s clock pins. after configura- tion on power-up, the registers either set or reset, depending on the user?s choice. the clocking scheme is designed to allow efficient use of multiple clocks with low clock skew, both within a column and across the core cell array.
15 at40kel040 4155e?aero?06/04 figure 10. clocking (for one column of cells) global clock line (buried) sector clock mux column clock mux sector clock mux express bus (plane 4; half length at edge) gck1 - gck8 repeater fck (2 per edge column of the array) ?1? ?1? ?1? ?1? } ? ? ?
16 at40kel040 4155e?aero?06/04 set/reset scheme the at40kel040 family reset scheme is essentially the same as the clock scheme except that there is only one global reset. a dedicated global set/reset bus can be driven by any user i/o, except those used for clocking (global clocks or fast clocks). the automatic placement tool will choose the reset net with the most connections to use the global resources. you can change this by using an rsbuf component in your design to indicate the global reset. additional resets will use the express bus network. the global set/reset is distributed to each column of the array. like sector clock mux, there is sector set/reset mux at every four cells. each sector column of four cells is set/reset by a plane 5 express bus or global set/reset using the sector set/reset mux (figure 11 on page 17). the set/reset provided to each sector column of four cells is either inverted or non-inverted using the sector reset mux. the function of the set/reset input of a r egister is determined by a configuration bit in each cell. the set/reset input of a register is active low (logic 0) by default. setting or resetting of a register is asynchronous. before configuration on power-up, a logic 1 (a high) is provided by each register (i.e., all registers are set at power-up).
17 at40kel040 4155e?aero?06/04 figure 11. set/reset (for one column of cells) each cell has a programmable set or reset global set/reset line (buried) repeater express bus (plane 5; half length at edge) sector set/reset mux any user i/o can drive global set/reset line ?1? ?1? ?1? ?1?
18 at40kel040 4155e?aero?06/04 i/o structure at40k has registered i/os and group enable every sector for tri-states on obuf?s. pad the i/o pad is the one that connects the i/o to the outside world. note that not all i/os have pads: the ones without pads are called unbonded i/os. the number of unbonded i/os varies with the device size and package. these unbonded i/os are used to perform a variety of bus turns at the edge of the array. pull-up/pull-down each pad has a programmable pull-up and pull-down attached to it. this supplies a weak ?1? or ?0? level to the pad pin. when all other drivers are off, this control will dictate the signal level of the pad pin. the input stage of each i/o cell has a number of parameters that can be programmed either as properties in schematic entry or in the i/o pad attributes editor in ids. cmos the threshold level is a cmos-compatible level. schmitt a schmitt trigger circuit can be enabled on the inputs. the schmitt trigger is a regenera- tive comparator circuit that adds 1v hysteresis to the input. this effectively improves the rise and fall times (leading and trailing edges) of the incoming signal and can be useful for filtering out noise. delays the input buffer can be programmed to include four different intrinsic delays as specified in the ac timing characteristics. this feat ure is useful for meeting data hold require- ments for the input signal. drive the output drive capabilities of each i/o ar e programmable. they can be set to fast, medium or slow (using ids tool). the fast setting has the highest drive capability (16 ma at 5v) buffer and the fastest slew rate. medium produces a medium drive (12 ma at 5v) buffer, while slow yields a standard (4 ma at 5v) buffer. tri-state the output of each i/o can be made tri-state (0, 1 or z), open source (1 or z) or open drain (0 or z) by programming an i/o?s source selection mux. of course, the output can be normal (0 or 1), as well. source selection mux the source selection mux selects the source for the output signal of an i/o. see figure 12 on page 21. primary, secondary and corner i/os the at40kel040 has three kinds of i/os: primary i/o, secondary i/o and a corner i/o. every edge cell except corner cells on the at40kel040 has access to one primary i/o and two secondary i/os. primary i/o every logic cell at the edge of the fpga array has a direct orthogonal connection to and from a primary i/o cell. the primary i/o interfaces directly to its adjacent core cell. it also connects into the repeaters on the row immediately above and below the adjacent core cell. in addition, each primary i/o also connects into the busing network of the three nearest edge cells. this is an extremely powerful feature, as it provides logic cells toward the center of the array with fast access to i/os via local and express buses. it can be seen from the diagram that a given primary i/o can be accessed from any logic cell on three separate rows or columns of the fpga. see figures 12a and 13a. secondary i/o every logic cell at the edge of the fpga array has two direct diagonal connections to a secondary i/o cell. the secondary i/o is located between core cell locations. this i/o
19 at40kel040 4155e?aero?06/04 connects on the diagonal inputs to the cell above and the cell below. it also connects to the repeater of the cell above and below. in addition, each secondary i/o also connects into the busing network of the two nearest edge cells. this is an extremely powerful fea- ture, as it provides logic cells toward the center of the array with fast access to i/os via local and express buses. it can be seen from the diagram that a given secondary i/o can be accessed from any logic cell on two rows or columns of the fpga. see figure 12a and figure 13b. corner i/o logic cells at the corner of the fpga array have direct-connect access to five separate i/os: 2 primary, 2 secondary and 1 corner i/o. corner i/os are like an extra secondary i/o at each corner of the array. with the inclusion of corner i/os, an at40kel040 fpga with n x n core cells always has 8n i/os. as the diagram shows, corner i/os can be accessed both from the corner logic cell and the horizontal and vertical busing net- works running along the edges of the array. this means that many different edge logic cells can access the corner i/os. see figure 14.
20 at40kel040 4155e?aero?06/04 figure 12. south i/o (mirrored for north i/o) vcc ttl/cmos gnd pull -up pad drive tri-state pull -down delay schmitt ?0? ?1? ?0? ?1? cell cell cell pad gnd pull -up pull -down ttl/cmos drive vcc tri-state delay schmitt ?0? ?1? ?1? ?0? cell cell (a) primary i/o source select mux source select mux (b) secondary i/o (a) primary i/o
21 at40kel040 4155e?aero?06/04 figure 13. west i/o (mirrored for east i/o) a. primary i/0 cell "0" "1" drive tri-state "0" "1" ttl/cmo s schmitt delay pull-down pull-up gnd vcc pad cell iclk rst rst oclk b. secondary i/o
22 at40kel040 4155e?aero?06/04 figure 14. northwest corner i/o (similar ne/se/sw corners) "0" "1" drive tri-state "0" "1" ttl/cmos schmitt delay pull-down pull-up gnd vcc pad "0" "1" drive tri-state "0" "1" ttl/cmo s schmitt delay pull-down pull-up gnd vcc pad "0" "1" drive tri-state "0" "1" ttl/cmos schmitt delay pull-down pull-up gnd vcc pad cell cell cell cell iclk rst iclk rst iclk rst rst rst oclk oclk rst rst oclk
23 at40kel040 4155e?aero?06/04 electrical characteristics absolute maximum ratings* operating temperature.................................. -55 c to +125 c *note: stresses beyond those listed under absolute maximum ratings may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those listed under oper- ating conditions is not implied. exposure to abso- lute maximum rating conditions for extended periods of time may affect device reliability. storage temperature ..................................... -65 c to +150 c junction temperature .................................................. +150 c voltage on any pin with respect to ground (1) ..........................-0.5v to v cc +0.5v 1. for dc input voltage (v i ) minimum voltage of -0.5v dc, which may undershoot to -2.0v for pulses of less than 20 ns. supply voltage (v cc ) .............................................3.3v 0.3v esd (r zap = 1.5k, c zap = 100 pf)................................. 4000v dc and ac operating range operating temperature -55 c to +125 c v cc power supply 3.3v 0.3v input voltage level (cmos) high (v ihc ) 70% - 100% v cc low (v ilc ) 0 - 30% v cc
24 at40kel040 4155e?aero?06/04 note: 1. parameter based on characterization and simulation; it is not tested in production. power-on power supply requirements atmel fpgas require a minimum rated power supply current capacity to ensure proper initialization, and the power supply ramp-up time does not affect the current required. a fast ramp-up time requires more current than a slow ramp-up time. table 3. power-on supply requirements note: 1. devices are guaranteed to initialize properly at 50% of the minimum current listed above. a larger capacity power supply may result in a larger initiallization current. 2. ramp-up time is measured from 0v dc to 3.6v dc. peak current required lasts less than 2 ms, and occurs near the internal power on reset threshold voltage. dc characteristics symbol parameter conditions min typ max units v ih high-level input voltage cmos 70% v cc v ttl 2.0 v v il low-level input voltage cmos -0.3 30% v cc v ttl -0.3 0.8 v v oh high-level output voltage i oh = -4 ma v cc = 3.0v 2.4 v i oh = -12 ma v cc = 3.0v 2.4 v i oh = -16 ma v cc = 3.0v 2.4 v v ol low-level output voltage i ol = +4 ma v cc = 3.0v 0.4 v i ol = +12 ma v cc = 3.0v 0.4 v i ol = +16 ma v cc = 3.0v 0.4 v i ih high-level input current v in = v cc max -5 5 a with pull-down, v in = v cc 20 75 300 a i il low-level input current v in = v ss -5 5 a with pull-up, v in = v ss -300.0 -50 -20 a i ozh high-level tri-state output leakage current without pull-down, v out = v cc max -5 5 a with pull-down, v out = v cc max 20 300 a i ozl low-level tri-state output leakage current without pull-up, v out = v ss -5 ma with pull-up, v out = v ss for con -500 -150.0 -110 a i cc standby current consumption standby, unprogrammed 1 5 ma c in input capacitance all pins 10 pf description maximum current (1)(2) maximum current supply 1.2 a
25 at40kel040 4155e?aero?06/04 ac timing characteristics delays are based on fixed loads and are described in the notes. maximum times based on worst case: v cc = 3.0v, temperature = 125c. minimum times based on best case: v cc = 3.60v, temperature = -55c. maximum delays are the average of t pdlh and t pdhl . ac timing characteristics all input i/o characteristics measured from v ih of 50% of v dd at the pad (cmos threshold) to the internal v ih of 50% of v dd . all output i/o characteristics are measured as the average of t pdlh and t pdhl to the pad v ih of 50% of v dd . cell function parameter path value units notes core 2-input gate t pd (max) x/y -> x/y 2.9 ns 1 unit load 3-input gate t pd (max) x/y/z -> x/y 3.1 ns 1 unit load 3-input gate t pd (max) x/y/w -> x/y 3.5 ns 1 unit load 4-input gate t pd (max) x/y/w/z -> x/y 3.5 ns 1 unit load fast carry t pd (max) y -> y 2.8 ns 1 unit load fast carry t pd (max) x -> y 2.6 ns 1 unit load fast crry t pd (max) y -> x 2.8 ns 1 unit load fast carry t pd (max) x -> x 2.9 ns 1 unit load fast carry t pd (max) w -> y 3.5 ns 1 unit load fast carry t pd (max) w -> x 3.5 ns 1 unit load fast carry t pd (max) z -> y 3.1 ns 1 unit load fast carry t pd (max) z -> x 3.0 ns 1 unit load dff t pd (max) clk -> x/y 4.3 ns 1 unit load dff t pd (max) r -> x/y 4.1 ns 1 unit load dff t pd (max) s -> x/y 2.8 ns 1 unit load dff t pd (max) q -> w 4.3 ns incremental -> l t pd (max) x/y -> l 2.5 ns 1 unit load local output enable t pzx (max) oe -> l 2.9 ns 1 unit load local output enable t pxz (max) oe -> l 0.9 ns cell function parameter path value units notes repeaters repeater t pd (max) l -> e 1.3 ns 1 unit load repeater t pd (max) e -> e 1.3 ns 1 unit load repeater t pd (max) l -> l 1.3 ns 1 unit load repeater t pd (max) e -> l 1.3 ns 1 unit load repeater t pd (max) e -> io 0.7 ns 1 unit load repeater t pd (max) l -> io 0.7 ns 1 unit load
26 at40kel040 4155e?aero?06/04 cell function parameter path value units notes i/o input t pd (max) pad -> x/y 5.4 ns no extra delay input t pd (max) pad -> x/y 7.6 ns 1 extra delay input t pd (max) pad -> x/y 11.4 ns 2 extra delays input t pd (max) pad -> x/y 14.9 ns 3 extra delays output, slow t pd (max) x/y/e/l -> pad 16.0 ns 50 pf load output, medium t pd (max) x/y/e/l -> pad 14.8 ns 50 pf load output, fast t pd (max) x/y/e/l -> pad 11.2 ns 50 pf load output, slow t pzx (max) oe -> pad 16.4 ns 50 pf load output, slow t pxz (max) oe -> pad 5.1 ns 50 pf load output, medium t pzx (max) oe -> pad 14.1 ns 50 pf load output, medium t pxz (max) oe -> pad 9.1 ns 50 pf load output, fast t pzx (max) oe -> pad 11.4 ns 50 pf load output, fast t pxz (max) oe -> pad 9.5 ns 50 pf load
27 at40kel040 4155e?aero?06/04 ac timing characteristics clocks and reset input buffers are measured from a v ih of 1.5v at the input pad to the internal v ih of 50% of v cc . maximum times for clock input buffers and internal drivers are measured for rising edge delays only. notes: 1. cmos buffer delays are measured from a v ih of 1/2 v cc at the pad to the internal v ih at a. the input buffer load is constant. 2. buffer delay is to a pad voltage of 1.5v with one output switching. 3. parameter based on characterization and simulation; not tested in production. 4. exact power calculation is available in atmel fpga designer software. cell function parameter path value units notes global clocks and set/reset gck input buffer t pd (max) pad -> clock 3.3 ns rising edge clock fck input buffer t pd (max) pad -> clock 1.9 ns rising edge clock clock column driver t pd (max) clock -> colclk 1.7 ns rising edge clock clock sector driver t pd (max) colclk -> secclk 0.8 ns rising edge clock gsrn input buffer t pd (max) colclk -> secclk 10.3 ns global clock to output t pd (max) clock pad -> out 21.3 ns rising edge clock fully loaded clock tree rising edge dff 20 ma output buffer 50 pf pin load fast clock to output t pd (max) clock pad -> out 19.9 ns rising edge clock fully loaded clock tree rising edge dff 20 ma output buffer 50 pf pin load
28 at40kel040 4155e?aero?06/04 ac timing characteristics cell function parameter path value units notes async ram write t wecyc (min) cycle time 28 ns write t wel (min) we 6.5 ns pulse width low write t weh (min) we 6.5 ns pulse width high write t setup (min) wr addr setup -> we 7.0 ns write t hold (min) wr addr hold -> we 0.0 ns write t setup (min) din setup -> we 6.5 ns write t hold (min) din hold -> we 0.0 ns write t hold (min) oe hold -> we 0.0 ns write/read t pd (max) din -> dout 14.1 ns rd addr = wr addr read t pd (max) rd addr -> dout 13.1 ns read t pzx (max) oe -> dout 4.5 ns read t pxz (max) oe -> dout 4.5 ns sync ram write t cyc (min) cycle time 28 ns write t clkl (min) clk 6.5 ns pulse width low write t clkh (min) clk 6.5 ns pulse width high write t setup (min) we setup -> clk 5.0 ns write t hold (min) we hold -> clk 0.0 ns write t setup (min) wr addr setup -> clk 6.5 ns write t hold (min) wr addr hold -> clk 0.0 ns write t setup (min) wr data setup -> clk 5.1 ns write t hold (min) wr data hold -> clk 0.0 ns write/read t pd (max) din -> dout 14.1 ns rd addr = wr addr write/read t pd (max) clk -> dout 7.9 ns rd addr = wr addr read t pd (max) rd addr -> dout 13.1 ns read t pzx (max) oe -> dout 4.5 ns read t pxz (max) oe -> dout 4.5 ns
29 at40kel040 4155e?aero?06/04 freeram asynchronous timing characteristics single port write/read dual port write with read dual port read
30 at40kel040 4155e?aero?06/04 freeram synchronous timing characteristics single port write/read dual port write with read we addr data t clkh t wcs t acs t dch t wch t ach 012 clk t oxz t dcs 3 oe t ozx t ad we wr addr wr data rd data t clkh t wcs t acs t cyc t wch t cd t ach = wr addr 1 rd addr 01 2 clk t clkl t dcs t dch
31 at40kel040 4155e?aero?06/04 dual port read rd addr data 01 t ozx oe t oxz t ad
at40kel040 32 4155e?aero?06/04 table 4. mqfp f-160 pin number signal 1vcc 2 i/o384_gck8_a15 3 i/o383_a14 4 i/o382 5 i/o381 6 i/o372_a13 7 i/o371_a12 8 i/o370 9 i/o369 10 gnd 11 i/o360 12 i/o359 13 i/o348_a11 14 i/o347_a10 15 i/o344 16 i/o343 17 i/o338_a9 18 i/o337_a8 19 vcc 20 gnd 21 i/o336_a7 22 i/o335_a6 23 i/o330 24 i/o329 25 i/o328 26 i/o326_a5 27 i/o325_a4 28 i/o314 29 i/o313 30 gnd 31 i/o304 32 i/o303 33 i/o298_a3 34 i/o297_cs1_a2 35 i/o292 36 i/o291 37 i/o290_gck7_a1 38 i/o289_a0 39 gnd 40 testclock 41 vcc 42 cclk 43 i/o288_gck6 44 i/o287_d0 45 i/o286 46 i/o285 47 i/o278 48 i/o277_d1 49 i/o274 50 i/o273 51 gnd 52 i/o262_fck4 53 i/o261 54 i/o260 55 i/o259_d2 56 i/o246 57 i/o245 58 i/o242_check 59 i/o241_d3 60 gnd 61 vcc 62 i/o240 63 i/o239_d4 64 i/o236 65 i/o235 66 i/o222_cs0 67 i/o221_d5 pin number signal 68 i/o220 69 i/o219_fck3 70 gnd 71 i/o208 72 i/o207 73 i/o206 74 i/o205_d6 75 i/o196 76 i/o195 77 i/o194_gck5 78 i/o193_d7 79 resetn 80 vcc 81 con 82 gnd 83 i/o192_gck4 84 i/o191_d8 85 i/o190 86 i/o189 87 i/o184_d9 88 i/o183_d10 89 i/o180 90 i/o179 91 gnd 92 i/o168 93 i/o167 94 i/o166_d11 95 i/o165_d12 96 i/o152 97 i/o151 98 i/o146_d13 99 i/o145_d14 100 gnd 101 vcc pin number signal
at40kel040 33 4155e?aero?06/04 102 i/o144_init 103 i/o143_d15 104 i/o138 105 i/o137 106 i/o124 107 i/o123 108 i/o122 109 i/o121 110 gnd 111 i/o110 112 i/o109 113 i/o102_ldc 114 i/o101 115 i/o100 116 i/o99 117 i/o98_hdc 118 i/o97_gck3 119 m2 120 vcc 121 m0 122 gnd 123 m1 124 i/o96_gck2 125 i/o95_ots 126 i/o94 127 i/o93 128 i/o90 129 i/o89 130 i/o84 131 i/o83 132 gnd 133 i/o72_fck2 134 i/o71 135 i/o70 pin number signal 136 i/o69 137 i/o54 138 i/o53 139 i/o50 140 i/o49 141 vcc 142 gnd 143 i/o48_a23 144 i/o47_a22 145 i/o44 146 i/o43 147 i/o28_a21 148 i/o27_a20 149 i/o26 150 i/o25_fck1 151 gnd 152 i/o16 153 i/o15 154 i/o6_a19 155 i/o5_a18 156 i/o4 157 i/o3 158 i/o2_a17 159 i/o1_gclk1_a16 160 gnd pin number signal
at40kel040 34 4155e?aero?06/04 table 5. mqfp - f256 pin number signal 1 io384_gck8_a15 2 io383_a14 3 io382 4 io381 5 io378 6 io377 7gnd 8vcc 9 io375 10 io374 11 io372_a13 12 io371_a12 13 io370 14 io369 15 io366 16 io365 17 io362 18 io360 19 io359 20 io358 21 io356 22 io355 23 io353 24 io352 25 io349 26 io348_a11 27 io347_a10 28 io346 29 io344 30 io343 31 io338_a9 32 io337_a8 33 io336_a7 34 io335_a6 35 io334 36 io330 37 io329 38 io328 39 io326_a5 40 io325_a4 41 io324 42 io323 43 io321 44 io320 45 io318 46 io317 47 io314 48 io313 49 io312 50 io311 51 io308 52 io307 53 io304 54 io303 55 io301 56 io298_a3 57 gnd 58 vcc 59 io297_cs1_a2 60 io291 61 io292 62 io290_gck7_a1 63 io289_a0 64 testclock 65 cclk 66 io288_gck6 67 io287_d0 pin number signal 68 io286 69 io285 70 io282 71 gnd 72 vcc 73 io278 74 io277_d1 75 io276 76 io274 77 io273 78 io272 79 io270 80 io269 81 io267 82 io266 83 io262_fck4 84 io261 85 io260 86 io259_d2 87 io258 88 io257 89 io254 90 io253 91 io252 92 io251 93 io248 94 io246 95 io245 96 io242_check 97 io241_d3 98 io240 99 io239_d4 100 io236 101 io235 pin number signal
at40kel040 35 4155e?aero?06/04 102 io234 103 io232 104 io230 105 io228 106 io227 107 io225 108 io224 109 io222_cs0 110 io221_d5 111 io220 112 io219_fck3 113 io216 114 io215 115 io212 116 io208 117 io207 118 io206 119 io205_d6 120 io204 121 gnd 122 vcc 123 io203 124 io196 125 io195 126 io194_gck5 127 io193_d7 128 resetn 129 con 130 io192_gck4 131 io191_d8 132 io190 133 io189 134 io186 135 gnd pin number signal 136 vcc 137 io184_d9 138 io183_d10 139 io181 140 io180 141 io179 142 io177 143 io174 144 io173 145 io171 146 io168 147 io167 148 io166_d11 149 io165_d12 150 io163 151 io162 152 io161 153 io158 154 io157 155 io156 156 io152 157 io151 158 io150 159 io149 160 io146_d13 161 io145_d14 162 io144_init 163 io143_d15 164 io141 138 io183_d10 139 io181 140 io180 141 io179 142 io177 pin number signal 143 io174 144 io173 145 io171 146 io168 147 io167 148 io166_d11 149 io165_d12 150 io163 151 io162 152 io161 153 io158 154 io157 155 io156 156 io152 157 io151 158 io150 159 io149 160 io146_d13 161 io145_d14 162 io144_init 163 io143_d15 164 io141 165 io138 166 io137 167 io136 168 io134 169 io132 170 io131 171 io129 172 io128 173 io124 174 io123 175 io122 176 io121 pin number signal
at40kel040 36 4155e?aero?06/04 177 io120 178 io119 179 io116 180 io115 181 io113 182 io110 183 io109 184 io101 185 gnd 186 vcc 187 io102_ldc 188 io99 189 io100 190 io98_hdc 191 io97_gck3 192 m2 193 m0 194 m1 195 io96_gck2 196 io95_ots 197 io94 198 io93 199 gnd 200 vcc 201 io90 202 io89 203 io86 204 io85 205 io84 206 io83 207 io80 208 io79 209 io77 210 io76 pin number signal 211 io72_fck2 212 io71 213 io70 214 io69 215 io67 216 io66 217 io63 218 io62 219 io60 220 io59 221 io57 222 io56 223 io54 224 io53 225 io50 226 io49 227 io48_a23 228 io47_a22 229 io44 230 io43 231 io41 232 io39 233 io36 234 io35 235 io34 236 io33 237 io30 238 io29 239 io28_a21 240 io27_a20 241 io26 242 io25_fck1 243 io21 244 io20 pin number signal 245 io18 246 io16 247 io15 248 io13 249 gnd 250 vcc 251 io6_a19 252 io5_a18 253 io4 254 io3 255 io2_a17 256 io1_gclk1_a16 pin number signal
37 at40kel040 4155e?aero?06/04 part/package availability and user i/o counts (including dual-function pins) note: 1. contact atmel for availability. package at40kel040 mqfpf 160 130 mqfpf 256 (1) 240
38 at40kel040 4155e?aero?06/04 ordering information notes: 1. contact atmel for availability part number package temperature range quality flow at40kel040kw1-e mqfpf160 25 c engineering samples 5962-0325001QXC mqfpf160 -55 to +125 cqml q 5962-0325001vxc mqfpf160 -55 to +125 cqml v at40kel040kw1sb mqfpf160 -55 to +125 c scc b at40kel040kz1-e (1) mqfpf256 25 c engineering samples 5962-0325001qyc (1) mqfpf256 -55 to +125 cqml q 5962-0325001vyc (1) mqfpf256 -55 to +125 cqml v at40kel040kz1sb (1) mqfpf256 -55 to +125 c scc b
39 at40kel040 4155e?aero?06/04 package drawing multilayer quad flat pack (mqfp) 160-pin
40 at40kel040 4155e?aero?06/04 multilayer quad flat pack (mqfp) 256-pin
41 at40kel040 4155e?aero?06/04 datasheet change log changes from 4155b - 06/03 to 4155c 04/04 1. addition of mqfp f256 package information 2. pad/ pin assignment updated. table 4 on page 31. 3. ordering information updated 4. reference to design tools changes from 4155c - 06/03 to 4155d 04/04 1. update of radiation hardness performance, page 1. changes from 4155d 04/04 - to 4155e 06/04 1. updated freeram timing characteristics, section ?freeram asynchronous tim- ing characteristics?, page 29.
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